1. Field of the Invention
Embodiments relate to a semiconductor device and a method of manufacturing the same. More particularly, embodiments relate to a fin field effect transistor (FinFET) and a method of manufacturing the same.
2. Description of the Related Art
A vast amount of research has lately been conducted on nano-CMOS device technology worldwide because the nano-CMOS device technology can be applied to logic circuits, such as a central processing unit (CPU), and memories to create high value-added products. With the downscaling of systems using silicon semiconductor technology and the increased demand for low power consumption, devices also need to shrink. Presently, the on-going downscaling in the gate size of devices gives rise to problems with, especially, a short channel effect (SCE).
Conventional CMOS technology involves forming CMOS devices on a bulk silicon substrate. When a MOS device formed on a bulk silicon substrate has a gate length of 50 nm or less, the characteristics of the MOS device are greatly affected by process conditions. A MOS device having a channel length of near 30 nm may still be insufficient for an actual circuit in terms of performance. Furthermore, an area occupied by a single actual device does not shrink due to an unreduced space region formed beside a gate, compared with a conventional device, so that the integration density of the device is not greatly improved.
Owing to a technical limit in MOS device technology based on a bulk silicon substrate, laborious research into a device formed on a silicon-on-insulator (SOI) substrate has progressed in order to form devices having a channel length of 30 nm or less. There have been extensive studies on the characteristics of a conventional device structure formed on a SOI substrate instead of a bulk silicon substrate. In the device structure formed on the SOI substrate, a parasitic source/drain resistance greatly increases due to the silicon layer having a small thickness, so that separate selective formation of an epitaxial layer in source and drain regions may be needed. Also, since a body of a SOI device is not connected to the substrate, the performance of the SOI device, for example, a floating body effect and thermal conductivity, may be degraded.
As described above, when a conventional device structure is formed on a SOI substrate, a SOI device is not appreciably shrunk compared with a conventional device based on a bulk silicon substrate. To solve this problem, a tri-gate structure or a dual-gate structure has been proposed to reduce a channel length of a CMOS device to 25 nm or less. The tri-gate structure or dual-gate structure is typically called a fin field effect transistor (FinFET). More specifically, when a channel region is formed on a protruding pattern, called a fin, having three surfaces (i.e., a top surface and two sidewalls) on a bulk silicon substrate, a tri-gate FinFET is obtained. Also, when a capping layer is formed on the fin of the tri-gate FinFET to cut off a vertical gate field effect and a channel region is formed on two surfaces (i.e., both sidewalls) of the fin, a dual-gate FinFET is manufactured.
In the foregoing FinFETs, since a gate electrode is formed on several surfaces of a channel region to which current is supplied, the channel region can be effectively controlled by the gate electrode. Thus, a leakage current flowing between source and drain regions can be greatly reduced compared with the conventional case, thereby markedly improving a drain induced barrier lowering (DIBL) effect. Furthermore, the gate electrode is formed on both sides of the channel region so that the threshold voltage of a device can be dynamically changed. As a result, the on-off characteristics of the channel region can be notably enhanced compared with a single gate structure, and the occurrence of an SCE can be inhibited. Therefore, further advances in FinFET devices and manufacture are desired.